In order to reduce the power consumption of a device such as a processor that is installed in an electronic device, a technology is known in which power saving of the entire processor is achieved using a transistor having only a small amount of leakage current, or a technology is known in which power saving is achieved in small units (hardware blocks) called modules that are used in implementing specific functions in the processor.
The technology of reducing the power consumption on a module-by-module basis is called power gating and is implemented to stop the supply of electrical power to the modules. Thus, power gating is available only when the modules are not in use. On the other hand, as far as the technology for reducing the power consumption during the usage of modules is concerned, dynamic voltage and frequency scaling (DVFS) is known in which the voltage and the clock cycle during operations is varied in a dynamic manner. Besides, a technology called clock gating is also available as a conventional power saving technology in which the power consumption is reduced by stopping the clock signals. In an identical manner to power gating, clock gating is also implemented to reduce the power consumption of the modules corresponding to idle functions.
Regarding the effect of reducing power consumption of the modules, power gating is more effective. However, prior to enable power gating, data in volatile memory (e.g. SRAM or registers, etc.) is necessarily to be saved. When the concerned module is to be used, it is necessarily to restore the data which is save in memories before power gating or initialize the concerned module. Consequently, power gating is accompanied by overheads. In contrast, in the case of clock gating, it is only necessary to stop the clock signals. Hence, although clock gating is less effective than power gating as far as the reduction in power consumption is concerned, there are no overheads during clock gating because no information needs to be saved. Thus, while reducing the power consumption of modules, whether to enable power gating or to enable clock gating is decided by taking into account the respective merits and demerits.
Herein, power gating as well as clock gating can be implemented only when it is known in advance that the modules are not in operation. However, for example, in a state in which the processor is waiting for an input from outside, it is not known when the input would be received. Hence, it becomes necessary to continue with the supply of electrical power and clock signals.
In the past, the development of power saving technology, such as power gating or DVFS, was carried out keeping in mind single processors. However, for example, in the case in which a processor communicates with other devices, it is not possible to know when another device would send data. For that reason, regarding the functions (modules) related to data reception, it is imperative to continue with the supply of electrical power that is required to receive data from other devices.